//fdma axi write---------------------------------------------- reg [M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr =0; //AXI4 写地址 reg axi_awvalid = 1'b0; //AXI4 写地有效 wire [M_AXI_DATA_WIDTH-1 : 0] axi_wdata ; //AXI4 写数据 wire axi_wlast ; //AXI4 写LAST信号 reg axi_wvalid = 1'b0; //AXI4 写数据有效 wire w_next = (M_AXI_WVALID & M_AXI_WREADY);//当valid ready信号都有效,代表AXI4数据传输有效 reg [8 :0] wburst_len = 1 ; //写传输的axi burst长度,代码会自动计算每次axi传输的burst 长度 reg [8 :0] wburst_cnt = 0 ; //每次axi bust的计数器 reg [15:0] wfdma_cnt = 0 ;//fdma的写数据计数器 reg axi_wstart_locked =0; //axi 传输进行中,lock住,用于时序控制 wire [15:0] axi_wburst_size = wburst_len * AXI_BYTES;//axi 传输的地址长度计算 assign M_AXI_AWID = M_AXI_ID; //写地址ID,用来标志一组写信号, M_AXI_ID是通过参数接口定义 assign M_AXI_AWADDR = axi_awaddr; assign M_AXI_AWLEN = wburst_len - 1;//AXI4 burst的长度 assign M_AXI_AWSIZE = clogb2(AXI_BYTES-1); assign M_AXI_AWBURST = 2'b01;//AXI4的busr类型INCR模式,地址递增 assign M_AXI_AWLOCK = 1'b0; assign M_AXI_AWCACHE = 4'b0010;//不使用cache,不使用buffer assign M_AXI_AWPROT = 3'h0; assign M_AXI_AWQOS = 4'h0; assign M_AXI_AWVALID = axi_awvalid; assign M_AXI_WDATA = axi_wdata; assign M_AXI_WSTRB = {(AXI_BYTES){1'b1}};//设置所有的WSTRB为1代表传输的所有数据有效 assign M_AXI_WLAST = axi_wlast; assign M_AXI_WVALID = axi_wvalid & fdma_wready;//写数据有效,这里必须设置fdma_wready有效 assign M_AXI_BREADY = 1'b1; //---------------------------------------------------------------------------- //AXI4 FULL Write assign axi_wdata = fdma_wdata; assign fdma_wvalid = w_next; reg fdma_wstart_locked = 1'b0; wire fdma_wend; wire fdma_wstart; assign fdma_wbusy = fdma_wstart_locked ; //在整个写过程中fdma_wstart_locked将保持有效,直到本次FDMA写结束 always @(posedge M_AXI_ACLK) if(M_AXI_ARESETN == 1'b0 || fdma_wend == 1'b1 ) fdma_wstart_locked <= 1'b0; else if(fdma_wstart) fdma_wstart_locked <= 1'b1; //产生fdma_wstart信号,整个信号保持1个 M_AXI_ACLK时钟周期 assign fdma_wstart = (fdma_wstart_locked == 1'b0 && fdma_wareq == 1'b1); //AXI4 write burst lenth busrt addr ------------------------------ //当fdma_wstart信号有效,代表一次新的FDMA传输,首先把地址本次fdma的burst地址寄存到axi_awaddr作为第一次axi burst的地址。如果fdma的数据长度大于256,那么当axi_wlast有效的时候,自动计算下次axi的burst地址 always @(posedge M_AXI_ACLK) if(fdma_wstart) axi_awaddr <= fdma_waddr; else if(axi_wlast == 1'b1) axi_awaddr <= axi_awaddr + axi_wburst_size ; //AXI4 write cycle ----------------------------------------------- axi_wstart_locked_r1, axi_wstart_locked_r2信号是用于时序同步 reg axi_wstart_locked_r1 = 1'b0, axi_wstart_locked_r2 = 1'b0; always @(posedge M_AXI_ACLK)begin axi_wstart_locked_r1 <= axi_wstart_locked; axi_wstart_locked_r2 <= axi_wstart_locked_r1; end // axi_wstart_locked的作用代表一次axi写burst操作正在进行中。 always @(posedge M_AXI_ACLK) if((fdma_wstart_locked == 1'b1) && axi_wstart_locked == 1'b0) axi_wstart_locked <= 1'b1; else if(axi_wlast == 1'b1 || fdma_wstart == 1'b1) axi_wstart_locked <= 1'b0; //AXI4 addr valid and write addr----------------------------------- always @(posedge M_AXI_ACLK) if((axi_wstart_locked_r1 == 1'b1) && axi_wstart_locked_r2 == 1'b0) axi_awvalid <= 1'b1; else if((axi_wstart_locked == 1'b1 && M_AXI_AWREADY == 1'b1)|| axi_wstart_locked == 1'b0) axi_awvalid <= 1'b0; //AXI4 write data--------------------------------------------------- always @(posedge M_AXI_ACLK) if((axi_wstart_locked_r1 == 1'b1) && axi_wstart_locked_r2 == 1'b0) axi_wvalid <= 1'b1; else if(axi_wlast == 1'b1 || axi_wstart_locked == 1'b0) axi_wvalid <= 1'b0;// //AXI4 write data burst len counter---------------------------------- always @(posedge M_AXI_ACLK) if(axi_wstart_locked == 1'b0) wburst_cnt <= 'd0; else if(w_next) wburst_cnt <= wburst_cnt + 1'b1; assign axi_wlast = (w_next == 1'b1) && (wburst_cnt == M_AXI_AWLEN); //fdma write data burst len counter---------------------------------- reg wburst_len_req = 1'b0; reg [15:0] fdma_wleft_cnt =16'd0; // wburst_len_req信号是自动管理每次axi需要burst的长度 always @(posedge M_AXI_ACLK) wburst_len_req <= fdma_wstart|axi_wlast; // fdma_wleft_cnt用于记录一次FDMA剩余需要传输的数据数量 always @(posedge M_AXI_ACLK) if( fdma_wstart )begin wfdma_cnt <= 1'd0; fdma_wleft_cnt <= fdma_wsize; end else if(w_next)begin wfdma_cnt <= wfdma_cnt + 1'b1; fdma_wleft_cnt <= (fdma_wsize - 1'b1) - wfdma_cnt; end //当最后一个数据的时候,产生fdma_wend信号代表本次fdma传输结束 assign fdma_wend = w_next && (fdma_wleft_cnt == 1 ); //一次axi最大传输的长度是256因此当大于256,自动拆分多次传输 always @(posedge M_AXI_ACLK)begin if(wburst_len_req)begin if(fdma_wleft_cnt[15:8] >0) wburst_len <= 256; else wburst_len <= fdma_wleft_cnt[7:0]; end else wburst_len <= wburst_len; end |
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