S03-CH02-aurora_8b10b光通信

module aurora_8b10b_FRAME_GEN

(

    // User Interface

    TX_D,

    TX_REM,    

    TX_SOF_N,      

    TX_EOF_N,

    TX_SRC_RDY_N,

    TX_DST_RDY_N,

    // System Interface

    USER_CLK,      

    RESET,

    CHANNEL_UP

);

//*****************************Parameter Declarations****************************

//***********************************Port Declarations*******************************

   // User Interface

output  [0:15]     TX_D;

output             TX_REM;

output             TX_SOF_N;

output             TX_EOF_N;

output             TX_SRC_RDY_N;

input              TX_DST_RDY_N;

      // System Interface

input              USER_CLK;

input              RESET;

input              CHANNEL_UP;

//***************************External Register Declarations***************************

reg                TX_SRC_RDY_N;

reg                TX_SOF_N;

reg                TX_EOF_N;    

//***************************Internal Register Declarations***************************

reg     [0:15]     data_lfsr_r;    

reg     [0:7]      frame_size_r;

reg     [0:7]      bytes_sent_r;

reg     [0:3]      ifg_size_r;

    //State registers for one-hot state machine

reg                idle_r;

reg                single_cycle_frame_r;

reg                sof_r;

reg                data_cycle_r;

reg                eof_r;    

wire               reset_c;

//*********************************Wire Declarations**********************************

wire               ifg_done_c;

    //Next state signals for one-hot state machine

wire               next_idle_c;

wire               next_single_cycle_frame_c;

wire               next_sof_c;

wire               next_data_cycle_c;

wire               next_eof_c;

    wire       dly_data_xfer;

    reg [4:0]  channel_up_cnt;

//*********************************Main Body of Code**********************************

  always @ (posedge USER_CLK)

  begin

    if(RESET)

        channel_up_cnt <= `DLY 5'd0;

    else if(CHANNEL_UP)

      if(&channel_up_cnt)

        channel_up_cnt <= `DLY channel_up_cnt;

      else

        channel_up_cnt <= `DLY channel_up_cnt + 1'b1;

    else

      channel_up_cnt <= `DLY 5'd0;

  end

  assign dly_data_xfer = (&channel_up_cnt);

  //Generate RESET signal when Aurora channel is not ready

  assign reset_c = RESET || !dly_data_xfer;

    //______________________________ Transmit Data  __________________________________   

    //Generate random data using XNOR feedback LFSR

    //随机数发生器

    always @(posedge USER_CLK)

        if(reset_c)

        begin

            data_lfsr_r          <=  `DLY    16'hABCD;  //random seed value

        end

        else if(!TX_DST_RDY_N && !idle_r)

        begin

            data_lfsr_r          <=  `DLY    {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},

                                data_lfsr_r[0:14]};

        end

    //Connect TX_D to the DATA LFSR

    assign  TX_D    =   {1{data_lfsr_r}};

    //Tie DATA LFSR to REM to generate random words

    assign  TX_REM  = data_lfsr_r[0:0];

    //Use a counter to determine the size of the next frame to send

    //frame_size_r 帧计数同时也是每一次帧发送的最大数据个数

    always @(posedge USER_CLK)

        if(reset_c)  

            frame_size_r    <=  `DLY    8'h00;

        else if(single_cycle_frame_r || eof_r)// 一个循环的开始或者一帧结束计数

            frame_size_r    <=  `DLY    frame_size_r + 1;

    //Use a second counter to determine how many bytes of the frame have already been sent

    //bytes_sent_r计数器计数一次帧传输发送的最大数据个数

    always @(posedge USER_CLK)

        if(reset_c)

            bytes_sent_r    <=  `DLY    8'h00;

        else if(sof_r)

            bytes_sent_r    <=  `DLY    8'h01;

        else if(!TX_DST_RDY_N && !idle_r)

            bytes_sent_r    <=  `DLY    bytes_sent_r + 1;

    //Use a freerunning counter to determine the IFG

    //这个就是一个计数器用来控制ifg_done_c这个变量

    always @(posedge USER_CLK)

        if(reset_c)

            ifg_size_r      <=  `DLY    4'h0;

        else

            ifg_size_r      <=  `DLY    ifg_size_r + 1;

    //IFG is done when ifg_size register is 0

    assign  ifg_done_c  =   (ifg_size_r == 4'h0);   

    //_____________________________ Framing State machine______________________________

    //Use a state machine to determine whether to start a frame, end a frame, send

    //data or send nothing

   //下面的状态机决定了是启动一个帧传输，还是发送一帧数据，或者发送数据，或者什么都不发送

    //State registers for 1-hot state machine

    always @(posedge USER_CLK)

        if(reset_c)

        begin

            idle_r                  <=  `DLY    1'b1;

            single_cycle_frame_r    <=  `DLY    1'b0;

            sof_r                   <=  `DLY    1'b0;

            data_cycle_r            <=  `DLY    1'b0;

            eof_r                   <=  `DLY    1'b0;

        end

        else if(!TX_DST_RDY_N)

        begin

            idle_r                  <=  `DLY    next_idle_c;//空闲状态

            single_cycle_frame_r    <=  `DLY    next_single_cycle_frame_c;//start aframe 第一帧数据的开始

            sof_r                   <=  `DLY    next_sof_c;//sof 一帧数据的开始

            data_cycle_r            <=  `DLY    next_data_cycle_c;//下一帧

            eof_r                   <=  `DLY    next_eof_c;

        end

    //Nextstate logic for 1-hot state machine

  //在bytes_sent_r值为1-15期间锁存包括single_cycle_frame_r，eof_r，idle_r信号到idle_r

  //满足条件是  ifg_done_c ==0（即bytes_sent_r计数器工作在1-15期间）

                                            //以下三种情况将产生idle_r

                                            //1)single_cycle_frame_r代表一帧新的数据开始

                                            //2）eof_r代表一帧传送完成   

                                            //3）idle_r代表空闲可以传输数据，在这里还起到所存作用

    assign  next_idle_c                 =   !ifg_done_c &&//ifg_done_c==0

                                            (single_cycle_frame_r || eof_r || idle_r);

 //满足条件是  ifg_done_c ！=0（即bytes_sent_r=0）并且frame_size_r==0（分复位后以及循环计数归0）

                                            //以下三种情况将产生single_cycle_frame_r

                                            //1)idle_r代表空闲可以传输数据；

                                            //2）single_cycle_frame_r 锁存作用

                                            //3）eof_r代表一帧传送完成

    assign  next_single_cycle_frame_c   =   (ifg_done_c && (frame_size_r == 0)) &&

                                            (idle_r || single_cycle_frame_r || eof_r);

 //在bytes_sent_r值为0的时候锁存包括single_cycle_frame_r，eof_r，idle_信号到sof_c                            

 //满足条件是  ifg_done_c ！=0（即bytes_sent_r=0）并且frame_size_r！=0

                                            //以下三种情况将产生sof_r

                                            //1)idle_r代表空闲；

                                            //2）single_cycle_frame_r 代表每个循环第一帧

                                           //3）eof_r代表一帧传送完成                                               

    assign  next_sof_c                  =   (ifg_done_c && (frame_size_r != 0)) &&

                                            (idle_r || single_cycle_frame_r || eof_r);

  // frame_size_r != bytes_sent_r的时候 锁存  sof_r 和data_cycle_r 到data_cycle_r                                

    assign  next_data_cycle_c           =   (frame_size_r != bytes_sent_r) &&

                                            (sof_r || data_cycle_r);

  //满足条件是  frame_size_r == bytes_sent_r的时候锁存sof_r和data_cycle_r到eof_c

                                         //以下两种情况将产生eof_r

                                         //1)sof_r代表一帧开始；

                                         //2）data_cycle_r 代表每个帧发送阶段                                                

    assign  next_eof_c                  =   (frame_size_r == bytes_sent_r) &&//一帧发送完毕

                                            (sof_r || data_cycle_r);//

    //Output logic for 1-hot state machine

    always @(posedge USER_CLK)

        if(reset_c)

        begin

            TX_SOF_N        <=  `DLY    1'b1;

            TX_EOF_N        <=  `DLY    1'b1;

            TX_SRC_RDY_N    <=  `DLY    1'b1;   

        end

        else if(!TX_DST_RDY_N)

        begin

            TX_SOF_N        <=  `DLY    !(sof_r || single_cycle_frame_r);//axi Stream 总线接口 sof

            TX_EOF_N        <=  `DLY    !(eof_r || single_cycle_frame_r);//axi Stream 总线接口 eof

            TX_SRC_RDY_N    <=  `DLY    idle_r;//axi Stream 总线接口valid

        end    

endmodule

module aurora_8b10b_FRAME_CHECK

(

    // User Interface

    RX_D,

    RX_REM,    

    RX_SOF_N,      

    RX_EOF_N,

    RX_SRC_RDY_N,

    // System Interface

    USER_CLK,      

    RESET,

    CHANNEL_UP,

    ERR_COUNT

);

//***********************************Port Declarations*******************************

   // User Interface

input   [0:15]     RX_D;

input              RX_REM;

input              RX_SOF_N;

input              RX_EOF_N;

input              RX_SRC_RDY_N;

      // System Interface

input              USER_CLK;

input              RESET;

input              CHANNEL_UP;

output  [0:7]      ERR_COUNT;

//***************************Internal Register Declarations***************************

// Slack registers

reg   [0:15]     RX_D_SLACK;

reg              RX_REM_1SLACK;

reg              RX_REM_2SLACK;

reg              RX_SOF_N_SLACK;

reg              RX_EOF_N_SLACK;

reg              RX_SRC_RDY_N_SLACK;

reg     [0:8]      err_count_r = 9'd0;

reg                data_in_frame_r;

reg                data_valid_r;

reg     [0:15]     RX_D_R;

reg     [0:15]     pdu_cmp_data_r;

    // RX Data registers

reg     [0:15]     data_lfsr_r;

//*********************************Wire Declarations**********************************

wire               reset_c;

wire    [0:15]     data_lfsr_concat_w;

wire               data_valid_c;

wire               data_in_frame_c;

wire               data_err_detected_c;

reg                data_err_detected_r;

//*********************************Main Body of Code**********************************

  //Generate RESET signal when Aurora channel is not ready

  assign reset_c = RESET;

// SLACK registers

always @ (posedge USER_CLK)

begin

  RX_D_SLACK          <= `DLY RX_D;

  RX_SRC_RDY_N_SLACK  <= `DLY RX_SRC_RDY_N;

  RX_REM_1SLACK       <= `DLY RX_REM;

  RX_REM_2SLACK       <= `DLY RX_REM;

  RX_SOF_N_SLACK      <= `DLY RX_SOF_N;

  RX_EOF_N_SLACK      <= `DLY RX_EOF_N;

end

    //______________________________ Capture incoming data ___________________________   

    //·is valid when RX_SRC_RDY_N is asserted and data is arriving within a frame

    //检测到有效数据

    assign  data_valid_c    =   data_in_frame_c && !RX_SRC_RDY_N_SLACK;

    //检测到一帧数据

    //Data is in a frame if it is a single cycle frame or a multi_cycle frame has started

    assign  data_in_frame_c  =   data_in_frame_r  ||  (!RX_SRC_RDY_N_SLACK && !RX_SOF_N_SLACK);

    //RX Data in the pdu_cmp_data_r register is valid

    //only if it was valid when captured and had no error

    //数据有效信号data_valid_r

    always @(posedge USER_CLK)

        if(reset_c)  

           data_valid_r    <=  `DLY    1'b0;

        else if(CHANNEL_UP)

           data_valid_r    <=  `DLY    data_valid_c && !data_err_detected_c;

        else

           data_valid_r    <=  `DLY    1'b0;

    //Start a multicycle frame when a frame starts without ending on the same cycle. End

    //the frame when an EOF is detected

    //帧有效

    always @(posedge USER_CLK)

        if(reset_c)  

            data_in_frame_r  <=  `DLY    1'b0;

        else if(CHANNEL_UP)

        begin

          if(!data_in_frame_r && !RX_SOF_N_SLACK && !RX_SRC_RDY_N_SLACK && RX_EOF_N_SLACK)

            data_in_frame_r  <=  `DLY    1'b1;

          else if(data_in_frame_r && !RX_SRC_RDY_N_SLACK && !RX_EOF_N_SLACK)

            data_in_frame_r  <=  `DLY    1'b0;

        end

    //Register and decode the RX_D data with RX_REM bus 对应于keep信号

    always @ (posedge USER_CLK)

    begin //对应axi_stream_last信号和axi_stream_vaild信号,同时有效代表最后一个数据       

      if((!RX_EOF_N_SLACK) && (!RX_SRC_RDY_N_SLACK))

      begin

        case(RX_REM_1SLACK)//RX_REM_1SLACK作用对应于 是axi_stream_keep

          1'd0 : RX_D_R <=  `DLY {RX_D_SLACK[0:7], 8'b0};//0-7 有效 8-15

          1'd1 : RX_D_R <=  `DLY RX_D_SLACK;// 0-15有效

          default : RX_D_R  <=  `DLY RX_D_SLACK;

endcase

      end

      else if(!RX_SRC_RDY_N_SLACK)//读取数据

        RX_D_R          <=  `DLY    RX_D_SLACK;

    end

    //Calculate the expected frame data

    //随机数发生部分的数据寄存，包括有效数据部分

    always @ (posedge USER_CLK)

    begin

      if(reset_c)

        pdu_cmp_data_r <= `DLY {1{16'hD5E6}};

      else if(CHANNEL_UP)

      begin

        if(data_valid_c && !RX_EOF_N_SLACK)

        begin

          case(RX_REM_2SLACK)

            1'd0 : pdu_cmp_data_r <=  `DLY {data_lfsr_concat_w[0:7], 8'b0};

            1'd1 : pdu_cmp_data_r <=  `DLY data_lfsr_concat_w;

            default : pdu_cmp_data_r <=  `DLY data_lfsr_concat_w;

  endcase

        end

        else if(data_valid_c)

          pdu_cmp_data_r <=  `DLY data_lfsr_concat_w;

        end

      end

    //generate expected RX_D using LFSR

    //产生和发送端口匹配的随机数列

    always @(posedge USER_CLK)

        if(reset_c)

        begin

            data_lfsr_r          <=  `DLY    16'hD5E6;  //random seed value

        end

        else if(CHANNEL_UP)

        begin

          if(data_valid_c)

           data_lfsr_r          <=  `DLY    {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},

                                data_lfsr_r[0:14]};

        end

        else

        begin

           data_lfsr_r          <=  `DLY    16'hD5E6;  //random seed value

        end

    assign data_lfsr_concat_w = {1{data_lfsr_r}};

    //___________________________ Check incoming data for errors __________________________

    //An error is detected when LFSR generated RX data from the pdu_cmp_data_r register,

    //does not match valid data from the RX_D port

    //比较数据是否和发送的一致

    assign  data_err_detected_c    = (data_valid_r && (RX_D_R != pdu_cmp_data_r));

    //We register the data_err_detected_c signal for use with the error counter logic

    //寄存error一次

    always @(posedge USER_CLK)

      data_err_detected_r    <=  `DLY    data_err_detected_c;

    //Compare the incoming data with calculated expected data.

    //Increment the ERROR COUNTER if mismatch occurs.

    //Stop the ERROR COUNTER once it reaches its max value (i.e. 255)

    //error计数器

    always @(posedge USER_CLK)

        if(CHANNEL_UP)

        begin

          if(&err_count_r)

            err_count_r       <=  `DLY    err_count_r;

          else if(data_err_detected_r)

            err_count_r       <=  `DLY    err_count_r + 1;

        end

else

        begin        

          err_count_r       <=  `DLY    9'd0;

end   

    //Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches

    //max value) to the module output

    assign  ERR_COUNT =   err_count_r[1:8];

endmodule          

module aurora_8b10b_LL_TO_AXI_EXDES #

(

    parameter            DATA_WIDTH         = 16, // DATA bus width

    parameter            STRB_WIDTH         = 2, // STROBE bus width

    parameter            USE_UFC_REM        = 0, // UFC REM bus width identifier

    parameter            USE_4_NFC          = 0, // 0 => PDU, 1 => NFC, 2 => UFC

    parameter            BC                 =  DATA_WIDTH/8, //Byte count

    parameter            REM_WIDTH          = 1 // REM bus width

)

(

    // LocalLink input Interface

    LL_IP_DATA,

    LL_IP_SOF_N,

    LL_IP_EOF_N,

    LL_IP_REM,

    LL_IP_SRC_RDY_N,

    LL_OP_DST_RDY_N,

    // AXI4-S output signals

    AXI4_S_OP_TVALID,

    AXI4_S_OP_TDATA,

    AXI4_S_OP_TKEEP,

    AXI4_S_OP_TLAST,

    AXI4_S_IP_TREADY

);

`define DLY #1

//***********************************Port Declarations*******************************

    // AXI4-Stream TX Interface

     output     [0:(DATA_WIDTH-1)]     AXI4_S_OP_TDATA;

     output     [0:(STRB_WIDTH-1)]     AXI4_S_OP_TKEEP;

    output                            AXI4_S_OP_TVALID;

    output                            AXI4_S_OP_TLAST;

    input                             AXI4_S_IP_TREADY;

    // LocalLink TX Interface

    input      [0:(DATA_WIDTH-1)]     LL_IP_DATA;

    input      [0:(REM_WIDTH-1)]      LL_IP_REM;

    input                             LL_IP_SOF_N;

    input                             LL_IP_EOF_N;

    input                             LL_IP_SRC_RDY_N;

    output                            LL_OP_DST_RDY_N;

 wire     [0:(STRB_WIDTH-1)]     AXI4_S_OP_TKEEP_i;

//*********************************Main Body of Code**********************************

   assign AXI4_S_OP_TDATA  = LL_IP_DATA;

    assign AXI4_S_OP_TKEEP = AXI4_S_OP_TKEEP_i ;

   assign AXI4_S_OP_TVALID = !LL_IP_SRC_RDY_N;

   assign AXI4_S_OP_TLAST  = !LL_IP_EOF_N;

   assign AXI4_S_OP_TKEEP_i  = (LL_IP_REM == 1'b1)? 2'b11:2'b10;

   assign LL_OP_DST_RDY_N  = !AXI4_S_IP_TREADY;

endmodule

module aurora_8b10b_AXI_TO_LL_EXDES #

(

    parameter            DATA_WIDTH         = 16, // DATA bus width

    parameter            STRB_WIDTH         = 2, // STROBE bus width

    parameter            BC                 =  DATA_WIDTH/8, //Byte count

    parameter            USE_4_NFC          = 0, // 0 => PDU, 1 => NFC, 2 => UFC

    parameter            REM_WIDTH          = 1 // REM bus width

)

(

    // AXI4-S input signals

    AXI4_S_IP_TX_TVALID,

    AXI4_S_IP_TX_TREADY,

    AXI4_S_IP_TX_TDATA,

    AXI4_S_IP_TX_TKEEP,

    AXI4_S_IP_TX_TLAST,

    // LocalLink output Interface

    LL_OP_DATA,

    LL_OP_SOF_N,

    LL_OP_EOF_N,

    LL_OP_REM,

    LL_OP_SRC_RDY_N,

    LL_IP_DST_RDY_N,

    // System Interface

    USER_CLK,

    RESET,

    CHANNEL_UP

);

`define DLY #1

//***********************************Port Declarations*******************************

    // AXI4-Stream Interface

    input   [0:(DATA_WIDTH-1)]     AXI4_S_IP_TX_TDATA;

    input   [0:(STRB_WIDTH-1)]     AXI4_S_IP_TX_TKEEP;

    input                          AXI4_S_IP_TX_TVALID;

    input                          AXI4_S_IP_TX_TLAST;

    output                         AXI4_S_IP_TX_TREADY;

    // LocalLink TX Interface

    output reg [0:(DATA_WIDTH-1)]  LL_OP_DATA;

    output reg [0:(REM_WIDTH-1)]   LL_OP_REM;

    output reg                     LL_OP_SRC_RDY_N;

    output reg                     LL_OP_SOF_N;

    output reg                     LL_OP_EOF_N;

    input                          LL_IP_DST_RDY_N;

    // System Interface

    input                          USER_CLK;

    input                          RESET;

    input                          CHANNEL_UP;

    reg                            new_pkt_r;

    wire                           new_pkt;

 wire   [0:(STRB_WIDTH-1)]     AXI4_S_IP_TX_TKEEP_i;

//*********************************Main Body of Code**********************************

   assign AXI4_S_IP_TX_TREADY = !LL_IP_DST_RDY_N;

     always @ (posedge USER_CLK)

    begin

      LL_OP_DATA = AXI4_S_IP_TX_TDATA;

    end

    assign AXI4_S_IP_TX_TKEEP_i =  AXI4_S_IP_TX_TKEEP;

    always @ (posedge USER_CLK)

    begin

      LL_OP_SRC_RDY_N = !AXI4_S_IP_TX_TVALID;

      LL_OP_EOF_N = !AXI4_S_IP_TX_TLAST;

      LL_OP_REM = (AXI4_S_IP_TX_TKEEP_i == 2'b10) ? 1'b0 : 1'b1;

      LL_OP_SOF_N  = ~ ( ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? ((new_pkt_r) ? 1'b0 : 1'b1) : (new_pkt && (!new_pkt_r)));

    end

   assign new_pkt = ( AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && AXI4_S_IP_TX_TLAST ) ? 1'b0 : ((AXI4_S_IP_TX_TVALID && AXI4_S_IP_TX_TREADY && !AXI4_S_IP_TX_TLAST ) ? 1'b1 : new_pkt_r);

always @ (posedge USER_CLK)

begin

  if(RESET)

    new_pkt_r <= `DLY 1'b0;

  else if(CHANNEL_UP)

    new_pkt_r <= `DLY new_pkt;

  else

    new_pkt_r <= `DLY 1'b0;

end

endmodule

module aurora_8b10b_TB;

//*************************Parameter Declarations**************************

    parameter       SIM_MAX_TIME  = 9500000; //To quit the simulation

    //125.0MHz GT Reference clock

parameter       CLOCKPERIOD_1 = 8.0 ;

parameter       CLOCKPERIOD_2 = 8.0 ;

//parameter       CLOCKPERIOD_1 = 8.0;

//parameter       CLOCKPERIOD_2 = 8.0;

parameter       DRP_CLOCKPERIOD = 10.000  ; //GT DRP Clock

parameter       INIT_CLOCKPERIOD = 20.0 ; // Board/System Clock

//************************Internal Register Declarations*****************************

    //Freerunning Clock

reg                reference_clk_1_n_r;

reg                reference_clk_2_n_r;

reg     drp_clk_r;

reg     init_clk_p;

    //Global signals

reg                gt_reset_in;

reg                gsr_r;

reg                gts_r;

reg                reset_i;

//********************************Wire Declarations**********************************

    //Freerunning Clock        

wire               reference_clk_1_p_r;

wire               reference_clk_2_p_r;         

wire    init_clk_n;

//Dut1

    //Error Detection Interface

wire               hard_err_1_i;        

wire               soft_err_1_i;        

wire               frame_err_1_i;        

    //Status

wire               channel_up_1_i;        

wire               lane_up_1_i;

    //GT Serial I/O

wire               rxp_1_i;

wire               rxn_1_i;

wire               txp_1_i;

wire               txn_1_i;

    // Error signals from the Local Link packet checker

wire    [0:7]      err_count_1_i;

//Dut2

    //Error Detection Interface

wire               hard_err_2_i;        

wire               soft_err_2_i;        

wire               frame_err_2_i;        

    //Status

wire               channel_up_2_i;        

wire               lane_up_2_i;

    //GT Serial I/O

wire               rxp_2_i;

wire               rxn_2_i;

wire               txp_2_i;

wire               txn_2_i;

    // Error signals from the Local Link packet checker

wire    [0:7]      err_count_2_i;

//*********************************Main Body of Code**********************************

    //_________________________Serial Connections________________

    assign   rxn_1_i      =    txn_2_i;

    assign   rxp_1_i      =    txp_2_i;

    assign   rxn_2_i      =    txn_1_i;

    assign   rxp_2_i      =    txp_1_i;

    //__________________________Global Signals_____________________________

    //Simultate the global reset that occurs after configuration at the beginning

    //of the simulation. Note that both GT smart models use the same global signals.

    assign glbl.GSR = gsr_r;

    assign glbl.GTS = gts_r;

    initial

        begin

            gts_r    = 1'b0;       

            gsr_r    = 1'b1;

            gt_reset_in = 1'b1;

            #5000;

            gsr_r    = 1'b0;

            gt_reset_in = 1'b0;

            repeat(10) @(posedge init_clk_p);

            gt_reset_in = 1'b1;

            repeat(10) @(posedge init_clk_p);

            gt_reset_in = 1'b0;

        end

    //____________________________Clocks____________________________

    initial

        reference_clk_1_n_r = 1'b0;

    always

        #(CLOCKPERIOD_1 / 2) reference_clk_1_n_r = !reference_clk_1_n_r;

    assign reference_clk_1_p_r = !reference_clk_1_n_r;

    initial

        reference_clk_2_n_r = 1'b0;

    always

        #(CLOCKPERIOD_2 / 2) reference_clk_2_n_r = !reference_clk_2_n_r;

    assign reference_clk_2_p_r = !reference_clk_2_n_r;

    initial

        drp_clk_r = 1'b0;

    always

        #(DRP_CLOCKPERIOD / 2) drp_clk_r = !drp_clk_r;

    initial

        init_clk_p = 1'b0;

    always

        #(INIT_CLOCKPERIOD / 2) init_clk_p = !init_clk_p;

    assign init_clk_n =  !init_clk_p;

    //____________________________Resets____________________________

    initial

    begin

        reset_i = 1'b1;

        #1000 reset_i = 1'b0;

    end

    //________________________Instantiate Dut 1 ________________

aurora_8b10b_exdes example_design_1_i

(

    // User IO

    .RESET(reset_i),

    // Error signals from Aurora   

    .HARD_ERR(hard_err_1_i),

    .SOFT_ERR(soft_err_1_i),

    .FRAME_ERR((frame_err_1_i)),

    // Status Signals

    .LANE_UP(lane_up_1_i),

    .CHANNEL_UP(channel_up_1_i),

    .INIT_CLK_P(init_clk_p),

    .INIT_CLK_N(init_clk_n),

    .DRP_CLK_IN(drp_clk_r),

    .GT_RESET_IN(gt_reset_in),

    // Clock Signals

    .GTXQ2_P(reference_clk_1_p_r),

    .GTXQ2_N(reference_clk_1_n_r),

    // GT I/O

    .RXP(rxp_1_i),

    .RXN(rxn_1_i),

    .TXP(txp_1_i),

    .TXN(txn_1_i),

    // Error signals from the Local Link packet checker

    .ERR_COUNT(err_count_1_i)

);

    //________________________Instantiate Dut 2 ________________

aurora_8b10b_exdes example_design_2_i

(

    // User IO

    .RESET(reset_i),

    // Error signals from Aurora   

    .HARD_ERR(hard_err_2_i),

    .SOFT_ERR(soft_err_2_i),

    .FRAME_ERR((frame_err_2_i)),

    // Status Signals

    .LANE_UP(lane_up_2_i),

    .CHANNEL_UP(channel_up_2_i),

    .INIT_CLK_P(init_clk_p),

    .INIT_CLK_N(init_clk_n),

    .DRP_CLK_IN(drp_clk_r),

    .GT_RESET_IN(gt_reset_in),

    // Clock Signals

    .GTXQ2_P(reference_clk_2_p_r),

    .GTXQ2_N(reference_clk_2_n_r),

    // GT I/O

    .RXP(rxp_2_i),

    .RXN(rxn_2_i),

    .TXP(txp_2_i),

    .TXN(txn_2_i),

    // Error signals from the Local Link packet checker

    .ERR_COUNT(err_count_2_i)

);

always @ (posedge channel_up_1_i or posedge channel_up_2_i)

begin

  if((channel_up_1_i == 1'b1) && (channel_up_2_i == 1'b1))

  begin

    $display("\naurora_8b10b_TB : INFO : @Time : %t CHANNEL_UP is asserted in both DUT\n", $time);

    #5000 $display("\naurora_8b10b_TB : INFO : Test Completed Successfully\n");

    $finish;

  end

end

always @ (posedge err_count_1_i[7] or posedge err_count_2_i[7])

begin

  if((err_count_1_i >= 8'b0000_0001) || (err_count_2_i >= 8'b0000_0001))

  begin  

    $display("\nAURORA_TB : ERROR : TEST FAIL\n");

    $display("\nAURORA_TB : INFO  : ERR_COUNT1 = %b ERR_COUNT2 = %b\n",err_count_1_i,err_count_2_i);

    #1000 $display("AURORA_TB : INFO : Exiting from simulation ....\n");

    $finish;

  end

end

//Abort the simulation when it reaches to max time limit

initial

begin

  #(SIM_MAX_TIME) $display("\nAURORA_TB : INFO : Reached max. simulation time limit\n");

  $finish;

end

endmodule

module aurora_8b10b_exdes #

(

     parameter   USE_CORE_TRAFFIC     = 1,

     parameter   USE_CHIPSCOPE        = 1

      //pragma translate_off

        & 0

      //pragma translate_on

)

(

    // User IO

    sys_rst_n,

INIT_CLK_IN,

sfp_tx_disable,

    GTXQ3_P,

GTXQ3_N,

    // GT I/O

    RXP,

    RXN,

    TXP,

    TXN

);

//***********************************Port Declarations*******************************

//***********************ADD****************************

output             sfp_tx_disable;

input              sys_rst_n;

input              INIT_CLK_IN;

//***********************ADD_END************************   

 // Clocks

input              GTXQ3_P;

input              GTXQ3_N;

    // GT Serial I/O

input              RXP;

input              RXN;

output             TXP;

output             TXN;

//********************************Wire Declarations**********************************

//***********************ADD****************************

wire              GT_RESET_IN;

wire              RESET;

assign GT_RESET_IN = ~sys_rst_n;

assign RESET = ~sys_rst_n;

assign sfp_tx_disable = 1'b0;

//***********************ADD_END************************

// LocalLink TX Interface

....

//*********************************Main Body of Code**********************************

//***********************ADD****************************

  IBUFG init_clk_bufg

   (.O   (init_clk_i),

    .I   (INIT_CLK_IN)

    );

assign drpclk_i =init_clk_i;

//***********************ADD_END************************....

create_clock -name GT_REFCLK1 -period 8.0  [get_ports GTXQ1_P]

####################### GT reference clock LOC #######################

set_property LOC D5 [get_ports GTXQ1_N]

set_property LOC D6 [get_ports GTXQ1_P]

set_property PACKAGE_PIN J13 [get_ports sys_rst_n]

set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]

# 10.0 ns period Board Clock Constraint

create_clock -name init_clk_i -period 10.0 [get_ports INIT_CLK_IN]

set_property PACKAGE_PIN AA3 [get_ports INIT_CLK_IN]

set_property IOSTANDARD LVCMOS15  [get_ports INIT_CLK_IN]

set_property PACKAGE_PIN D9 [get_ports sfp_tx_disable]

set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable]

###### CDC in RESET_LOGIC from INIT_CLK to USER_CLK ##############

set_false_path -to [get_pins -hier *aurora_8b10b_cdc_to*/D]

set_property LOC GTXE2_CHANNEL_X0Y4 [get_cells aurora_module_i/inst/aurora_8b10b_0_core_i/gt_wrapper_i/aurora_8b10b_0_multi_gt_i/gt0_aurora_8b10b_0_i/gtxe2_i]

connect_debug_port dbg_hub/clk [get_nets init_clk_i]