USB3.0 HDMI输入方案之FT601Q 1080P

module ft60x(

// system control

input                  Rstn_i,//fpga reset

output                 USBSS_EN,//power enable   

// FIFO interface    

input                  CLK_i,

inout [31:0]           DATA_io,

inout [3:0]            BE_io,

input                  RXF_N_i,   // ACK_N

input                  TXE_N_i,

output                 OE_N_o,

output                 WR_N_o,    // REQ_N

output                 SIWU_N_o,

output                 RD_N_o,

output                 WAKEUP_o,

output [1:0]           GPIO_o,

output                 usb_rd_en,

output                 usb_frame,

input  [31:0]          usb_data     

);

assign USBSS_EN = 1'b1;   

assign WAKEUP_o = 1'b1;

assign GPIO_o   = 2'b00;   

assign SIWU_N_o = 1'b0;

wire rstn;

(*mark_debug = "true"*) wire            usb_rd_en;

(*mark_debug = "true"*) wire            usb_frame;

(*mark_debug = "true"*) wire            RXF_N_i;   // ACK_N

(*mark_debug = "true"*) wire            TXE_N_i;

(*mark_debug = "true"*) reg             OE_N_o;

(*mark_debug = "true"*) reg             WR_N_o;    // REQ_N

(*mark_debug = "true"*) reg             RD_N_o;

(*mark_debug = "true"*) (* KEEP = "TRUE" *)wire [31:0] rd_data;

(*mark_debug = "true"*) (* KEEP = "TRUE" *)wire [31:0] wr_data;

(*mark_debug = "true"*) wire [3 :0] BE_RD;

(*mark_debug = "true"*) wire [3 :0] BE_WR;

(*mark_debug = "true"*) reg [1:0] USB_S;

wire data_rd_valid,data_wr_valid;

assign data_rd_valid = (RD_N_o==1'b0)&&(RXF_N_i==1'b0);

assign data_wr_valid = (WR_N_o==1'b0)&&(TXE_N_i==1'b0);

//read or write flag

assign rd_data  =  (USB_S==2'd1) ? DATA_io : 32'd0;//read data dir

assign BE_RD    =  (USB_S==2'd1) ? BE_io   : 4'd0;

assign DATA_io  =  (USB_S==2'd2) ? wr_data : 32'bz;// write data dir

assign BE_io    =  (USB_S==2'd2) ? BE_WR   : 4'bz;// write data dir

assign BE_WR    =  4'b1111;

assign wr_data = usb_data;

(*mark_debug = "true"*) (* KEEP = "TRUE" *) reg [15:0]rd_cnt;

(*mark_debug = "true"*) (* KEEP = "TRUE" *) reg [31:0] fram_cmd;

always @(posedge CLK_i)begin

    if(!rstn)begin

        fram_cmd <= 32'd0;

    end

    else if(data_rd_valid) begin

        fram_cmd <= rd_data;

    end

    else begin

        if(fram_cmd> 32'd0)begin

            fram_cmd <= fram_cmd - 1'b1;

        end

    end

end

assign usb_frame = (fram_cmd> 32'd2000);

assign usb_rd_en = data_wr_valid;

always @(posedge CLK_i)begin

    if(!rstn)begin

        USB_S <= 2'd0;

        OE_N_o <= 1'b1;

        RD_N_o <= 1'b1;

        WR_N_o <= 1'b1;

    end

    else begin

        case(USB_S)

        0:begin

            OE_N_o <= 1'b1;

            RD_N_o <= 1'b1;

            WR_N_o <= 1'b1;

            if((!RXF_N_i)) begin

                USB_S  <= 2'd1;

                OE_N_o <= 1'b0;  

            end

            else if((!TXE_N_i))begin

                USB_S  <= 2'd2;

            end

        end

        1:begin

            RD_N_o <= 1'b0;  

            if(RXF_N_i) begin

                USB_S  <= 2'd0;

                RD_N_o <= 1'b1;

                OE_N_o <= 1'b1;     

            end

        end

        2:begin

            WR_N_o <= 1'b0;

            if(TXE_N_i) begin

                USB_S  <= 2'd0;

                WR_N_o <= 1'b1;

             end

        end

        3:begin

            USB_S <= 2'd0;

        end

        endcase                

    end

end

Delay_rst_0 Delay_rst_inst

(

    .clk_i(CLK_i),

    .rstn_i(Rstn_i),

    .rst_o(rstn)

 );

endmodule