SDI种embedded_synchronous模块的疑问

always@(posedge clk)
begin
bt656_in_d0 <= embedded_data_in[19:12];
bt656_in_d1 <= bt656_in_d0;
bt656_in_d2 <= bt656_in_d1;
bt656_in_d3 <= bt656_in_d2;
bt656_in_d4 <= bt656_in_d3;
trs_d0 <= trs;
trs_d1 <= trs_d0;
rx_eav_d0 <= rx_eav;
rx_eav_d1 <= rx_eav_d0;
end

always@(posedge clk)
begin
yc_data_tmp_d0 <= yc_data_tmp;
yc_data_tmp_d1 <= yc_data_tmp_d0;//DATA1对应de_p
yc_data_tmp_d2 <= yc_data_tmp_d1;
yc_data_tmp_d3 <= yc_data_tmp_d2;
de_t_d0 <= de_t;
de_t_d1 <= de_t_d0;
de_t_d2 <= de_t_d1;
de_t_d3 <= de_t_d2;
end

模块种对数据这样接8位数据这样处理怎么理解？

凡帆 · 发表于 2021-11-14 23:34:48

对这个模块这样处理不是很明白，是否可以讲解一下

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