Vivado:2018.3
纯PL,模块完成功能,获取ADC数据,并缓存(64个模拟数据,分时采集),将指定缓存数据输出。
定义缓存数组:reg [13:0] AnalogData [63:0];
综合时出现Warning:[Netlist 29-101] Netlist '顶层模块名称' is not ideal for floorplanning, since the cellview '该模块名称' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
这个Waring该怎么消除?
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