PL 通过DMA向PS发送数据，数据无法刷新

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本帖最后由 demo3010 于 2018-9-2 09:56 编辑

1.模型设计，PL向PS发送数据（连续相加的数1~65535，然后循环）
实验结果，PS内存中的第一个数始终为03020100，没有刷新。理论上该数应该是变化的。

PL：代码如下：
always@(posedge SysClk) begin
      if(SysRst == 1'B1) begin
         S_AXIS_tvalid  <= 1'b0;
         S_AXIS_tdata <= 16'd0;
         S_AXIS_tlast <= 1'b0;
         dataDeep    <= 11'b0;
         dataTest    <= 16'b0;
         state       <=0;
      end
      else begin
         case(state)
         0: begin
            if(dataStart_En && S_AXIS_tready) begin
                  S_AXIS_tvalid  <= 1'b1;
                  state       <= 1;
            end
            else begin
                  S_AXIS_tvalid  <= 1'b0;
                  state       <= 0;
            end
            end
         1:begin
            if(S_AXIS_tready) begin
                  dataDeep       <= dataDeep + 1'b1;
                  dataTest       <= dataTest + 1'b1;
                  S_AXIS_tdata <= dataTest;
                  if(dataDeep == 16'd1022) begin
                     S_AXIS_tlast <= 1'b1;
                     state          <= 2;
                  end
                  else begin
                     S_AXIS_tlast <= 1'b0;
                     state          <= 1;
                  end
            end
            else begin
                  S_AXIS_tdata <= S_AXIS_tdata;
                  dataDeep       <= dataDeep;
                  state          <= 1;
            end
         end
         2:begin
            if(!S_AXIS_tready) begin
               S_AXIS_tvalid <= 1'b1;
               S_AXIS_tlast    <= 1'b1;
               S_AXIS_tdata    <= S_AXIS_tdata;
               dataDeep       <= dataDeep;
               state          <= 2;
            end
            else begin
               S_AXIS_tvalid <= 1'b0;
               S_AXIS_tlast    <= 1'b0;
               S_AXIS_tdata    <= 16'd0;
               dataDeep       <= 11'b0;
               state          <= 0;
            end
         end
         default: state <=0;
         endcase
      end
end

PS：代码如下：
int init_intr_sys(void)
{
DMA_Intr_Init(&AxiDma,0);//initial interrupt system
Timer_init(&Timer,TIMER_LOAD_VALUE,0);
Init_Intr_System(&Intc); // initial DMA interrupt system
Setup_Intr_Exception(&Intc);
DMA_Setup_Intr_System(&Intc,&AxiDma,TX_INTR_ID,RX_INTR_ID);//setup dma interrpt system
Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR);
DMA_Intr_Enable(&Intc,&AxiDma);

}

int main(void)
{
init_intr_sys();
axi_dma_test();

}

int axi_dma_test()
{
int Status;
TxDone = 0;
RxDone = 0;
Error = 0;

xil_printf("123");

xil_printf("PKT_LEN=%d\r\n",MAX_PKT_LEN);

for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
         TxBufferPtr[Index] = Value;

         Value = (Value + 1) & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
   * is enabled
   */
Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN);
Timer_start(&Timer);
while(1)
//for(i = 0; i < Tries; i ++)
{
      //RX DMA Transfer
      if (first)
      {
            Status = XAxiDma_SimpleTransfer(&AxiDma,(u32)RxBufferPtr,
                     (u32)(MAX_PKT_LEN), XAXIDMA_DEVICE_TO_DMA);

            if (Status != XST_SUCCESS) {return XST_FAILURE;}
            first = 0;
      }

      if(RX_ready)
      {
         RX_ready=0;
      }

      //TX DMA Transfer
      if(TX_ready)
      {
         TX_ready=0;
         Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr,
                  (u32)(MAX_PKT_LEN), XAXIDMA_DMA_TO_DEVICE);

         if (Status != XST_SUCCESS) {return XST_FAILURE;}
      }

      if(RxDone)
      {
         RxDone=0;
         RX_ready=1;
         RX_success++;
      }

      if(TxDone)
      {
         TxDone=0;
         TX_ready=1;
         TX_success++;
      }
      if(usec==2)
      {

         usec=0;
         sprintf(oled_str,"RX=%d",RX_success);
         xil_printf("%s\r\n",oled_str);

         speed_rx = MAX_PKT_LEN*RX_success/1024/1024;

         sprintf(oled_str,"RX_sp=%.2fMB/S",speed_rx);
         xil_printf("%s\r\n",oled_str);

         sprintf(oled_str,"TX=%d",TX_success);
         xil_printf("%s\r\n",oled_str);

         speed_tx = (MAX_PKT_LEN)*TX_success/1024/1024;

         sprintf(oled_str,"TX_sp=%.2fMB/S",speed_tx);
         xil_printf("%s\r\n",oled_str);

         RX_success=0;
         TX_success=0;

      }

      if (Error) {
         xil_printf("Failed test transmit%s done, "
         "receive%s done\r\n", TxDone? "":" not",
                        RxDone? "":" not");
         goto Done;
      }

}

/* Disable TX and RX Ring interrupts and return success */
DMA_DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
Done:
xil_printf("--- Exiting Test --- \r\n");
return XST_SUCCESS;

}

lsw0136 · 发表于 2018-11-14 16:04:47

楼主解决了吗？我也遇到这个问题了，看仿真信号PL端一直到PS端HP口数据都在变化，读到内存里的就是不变的，不知道什么原因啊。

demo3010 · 发表于 2018-11-21 11:09:22

lsw0136 发表于 2018-11-14 16:04
楼主解决了吗？我也遇到这个问题了，看仿真信号PL端一直到PS端HP口数据都在变化，读到内存里的就是不变的， ...

需要刷新 cache
Xil_DCacheFlushRange((u32)addr, 131072);

ruiyang89 · 发表于 2019-1-9 09:21:39

SDK上貌似不能全速运行，点一下暂停看一下

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