请教一个延时模块的问题

mkelehk · 发表于 2016-8-28 01:12:47

搞不明白下面延时模块注释部分与当前部分有什么区别，使用当前代码仿真时，count是x，使用注释部分却正常！！
module system_delay
#(
      parameter SYS_DELAY_TOP = 23'd2500000       //50ms
)
(
      input clk,
      input rst_n,

      output delay_done
);

reg [22:0] count;
always @ (posedge clk or negedge rst_n)

/*
begin
      if(!rst_n)
            count <= 23'd0;
      else if(count < SYS_DELAY_TOP - 1'b1)
            count <= count + 1'b1;
      else
            count <= SYS_DELAY_TOP - 1'b1;
end

assign delay_done = (count == SYS_DELAY_TOP - 1'b1)? 1'b1 : 1'b0;
*/

begin
      if(!rst_n)
            count <= 23'd0;
      else if(count == SYS_DELAY_TOP)
            count <= SYS_DELAY_TOP;
      else
            count <= count + 1'b1;
end

assign delay_done = (count == SYS_DELAY_TOP)? 1'b1 : 1'b0;

endmodule