always @(posedge c3_clk0)
begin
if(c3_rst0 || !c3_calib_done)
begin
c3_p1_rd_en<=1'b0;
c3_p1_cmd_en<=1'b0;
c3_p1_cmd_instr<=3'd0;
c3_p1_cmd_bl<=6'd0;
c3_p1_cmd_byte_addr<=30'd0;
ddr_read_state<=read_idle;
wav_out_data<=64'd0;
end
else begin
case(ddr_read_state)
read_idle:begin
if(wav_rden_req==1'b1) begin //如果有ddr读请求
ddr_read_state<=read_cmd_start;
end
end
read_cmd_start:begin
c3_p1_cmd_en<=1'b0;
c3_p1_cmd_instr<=3'b001; //命令字为读
c3_p1_cmd_bl<=6'd0; //single read
ddr_read_state<=read_cmd;
end
read_cmd:begin
c3_p1_cmd_en<=1'b1; //ddr读命令使能
ddr_read_state<=read_wait;
end
read_wait:begin
c3_p1_cmd_en<=1'b0;
if(!c3_p1_rd_empty) //如果read fifo不空
ddr_read_state<=read_data;
end
read_data:begin
c3_p1_rd_en<=1'b1; //读数据使能
ddr_read_state<=read_done;
wav_out_data<=c3_p1_rd_data;
end
read_done:begin
c3_p1_rd_en<=1'b0;
ddr_read_state<=read_idle;
c3_p1_cmd_byte_addr<=c3_p1_cmd_byte_addr+8;
end
default:begin
c3_p1_rd_en<=1'b0;
c3_p1_cmd_en<=1'b0;
ddr_read_state<=read_idle;
end
endcase;
end
end
为什么程序中的读数据就几个周期，而shipscope抓信号显示十几个周期 困惑。。。。。。。。
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