序号 | DB9公头 | DB9母头 | ||
1 | CD | 载波检测 | CD | 载波检测 |
2 | RXD | 接收端接收 | TXD | 发送端发送数据 |
3 | TXD | 发送数据 | RXD | 接收端接收数据 |
4 | DTR | 数据终端就绪 | DTR | 数据终端就绪 |
5 | GND | 系统接地 | GND | 系统接地 |
6 | DSR | 数据准备就绪 | DSR | 数据准备就绪 |
7 | RTS | 发送请求 | CTS | 清除请求 |
8 | CTS | 清除发送 | RTS | 发送请求 |
9 | RI | 振铃指示器 | RI | 振铃指示器 |
`timescale 1ns / 1ns module uart_top ( input sysclk_i, input uart_rx_i, output uart_tx_o ); reg [11:0] rstn_cnt = 0; wire uart_rstn_i; wire uart_wreq,uart_rvalid; wire [7:0]uart_wdata,uart_rdata; assign uart_wreq = uart_rvalid; assign uart_wdata = uart_rdata; assign uart_rstn_i = rstn_cnt[11]; always @(posedge sysclk_i)begin if(rstn_cnt[11] == 1'b0) rstn_cnt <= rstn_cnt + 1'b1; else rstn_cnt <= rstn_cnt; end //uart send controller uiuart_tx# ( .BAUD_DIV(25000000/115200 -1) ) uart_tx_u ( .clk_i(sysclk_i), .uart_rstn_i(uart_rstn_i), .uart_wreq_i(uart_wreq), .uart_wdata_i(uart_wdata), .uart_wbusy_o(), .uart_tx_o(uart_tx_o) ); uiuart_rx# ( .BAUD_DIV(25000000/115200 -1) ) uiuart_rx_u ( .clk_i(sysclk_i), .uart_rx_rstn_i(uart_rstn_i), .uart_rx_i(uart_rx_i), .uart_rdata_o(uart_rdata), .uart_rvalid_o(uart_rvalid) ); endmodule |
`timescale 1ns / 1ns module uart_top_TB; reg sysclk_i; reg uart_rx_i; wire uart_tx_o; uart_top u_uart_top ( .sysclk_i (sysclk_i), .uart_rx_i (uart_rx_i), .uart_tx_o (uart_tx_o) ); parameter FREQ = 25000000; parameter BAUD = 115200; parameter TBAUD = FREQ/BAUD*40; initial begin sysclk_i = 0; uart_rx_i = 1'b1; #200000 // Wait for global reset to finish #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b0;//start //1001_0101 #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b1;//stop #808320 //00000101 uart_rx_i = 1'b0;//start #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b1;//stop #808320 //10000100 uart_rx_i = 1'b0;//start #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b0; #TBAUD uart_rx_i = 1'b1; #TBAUD uart_rx_i = 1'b1;//stop end always begin #20 sysclk_i = ~sysclk_i; end endmodule |
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