AXI4总线 SLAVE部分 的 用户段 谁来解释一下呢？
// ------------------------------------------// -- Example code to access user logic memory region
// ------------------------------------------
generate
if (USER_NUM_MEM >= 1)
begin
assign mem_select= 1;
assign mem_address = (axi_arv_arr_flag? axi_araddr:(axi_awv_awr_flag? axi_awaddr:0));
end
endgenerate
// implement Block RAM(s)
generate
for(i=0; i<= USER_NUM_MEM-1; i=i+1)
begin:BRAM_GEN
wire mem_rden;
wire mem_wren;
assign mem_wren = axi_wready && S_AXI_WVALID ;
assign mem_rden = axi_arv_arr_flag ; //& ~axi_rvalid
for(mem_byte_index=0; mem_byte_index<= (C_S_AXI_DATA_WIDTH/8-1); mem_byte_index=mem_byte_index+1)
begin:BYTE_BRAM_GEN
wire data_in ;
wire data_out;
reg byte_ram ;
integerj;
//assigning 8 bit data
assign data_in= S_AXI_WDATA[(mem_byte_index*8+7) -: 8];
assign data_out = byte_ram;
always @( posedge S_AXI_ACLK )
begin
if (mem_wren && S_AXI_WSTRB)
begin
byte_ram <= data_in;
end
end
always @( posedge S_AXI_ACLK )
begin
if (mem_rden)
begin
mem_data_out[(mem_byte_index*8+7) -: 8] <= data_out;
end
end
end
end
endgenerate
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