`timescale 1ns / 1ps /*******************************MILIANKE******************************* *Company : MiLianKe Electronic Technology Co., Ltd. *Create Date: 2021/10/15 *Module Name: *File Name: *Description: *config sensor resgister *The reference demo provided by Milianke is only used for learning. *We cannot ensure that the demo itself is free of bugs, so users *should be responsible for the technical problems and consequences *caused by the use of their own products. *Copyright: Copyright (c) MiLianKe *All rights reserved. *Revision: 1.0 *Signal description *1) _i input *2) _o output *3) _n activ low *4) _dg debug signal *5) _r delay or register *6) _s state mechine *********************************************************************/ module fdma_ddr_test( output [14:0]DDR3_0_addr, output [2 :0]DDR3_0_ba, output DDR3_0_cas_n, output [0 :0]DDR3_0_ck_n, output [0 :0]DDR3_0_ck_p, output [0 :0]DDR3_0_cke, output [0 :0]DDR3_0_cs_n, output [3 :0]DDR3_0_dm, inout [31:0]DDR3_0_dq, inout [3:0]DDR3_0_dqs_n, inout [3:0]DDR3_0_dqs_p, output [0 :0]DDR3_0_odt, output DDR3_0_ras_n, output DDR3_0_reset_n, output DDR3_0_we_n, input sysclk_p );
wire resetn,init_calib_complete_0; wire wr_rd_clk; wire ud_rempty_0,error; reg ud_wvs_0, ud_wde_0 ,ud_rvs_0 ; wire [31:0]ud_wdata_0 , ud_rdata_0; reg [15:0]wr_cnt , rd_cnt, delay_cnt;
assign ud_rde_0 = !ud_rempty_0; assign ud_wdata_0 = {16'd0,wr_cnt};
assign resetn = init_calib_complete_0;
always @(posedge wr_rd_clk)begin if(resetn == 1'b0)begin delay_cnt <= 0; ud_rvs_0 <= 1'b0; end else if(delay_cnt[13:12] == 2'b11) begin //DDR初始化后，通过delay_cnt控制写入和读出的开始时机 delay_cnt <= delay_cnt; ud_rvs_0 <= 1'b1; end else begin delay_cnt <= delay_cnt + 1'b1; end end
//写数据启动部分代码 always @(posedge wr_rd_clk)begin if(delay_cnt[13] == 1'b0)begin //DDR初始化后，通过delay_cnt控制写入和读出的开始时机 ud_wvs_0 <= 1'b0; ud_wde_0 <= 1'b0; end else begin ud_wvs_0 <= 1'b1; ud_wde_0 <= 1'b1; end end
//写入16bits计数器值到缓存中 always @(posedge wr_rd_clk)begin if(resetn == 1'b0)begin wr_cnt <= 0; end else begin if(ud_wde_0) wr_cnt <= wr_cnt + 1'b1; end end
//当读信号ud_rde有效，通过计数器计数 always @(posedge wr_rd_clk)begin if(resetn == 1'b0)begin rd_cnt <= 0; end else begin if(ud_rde_0) rd_cnt <= rd_cnt + 1'b1; else rd_cnt <= rd_cnt; end end
//通过读出的数据和我们读计数器的值是否一致判断数据是否真确 assign error = ud_rde_0&&(rd_cnt != ud_rdata_0[15:0]);
//通过ILA观察数据 ila_0 your_instance_name ( .clk(wr_rd_clk), // input wire clk .probe0({ud_rde_0,rd_cnt,ud_rdata_0[15:0],ud_wde_0,ud_wdata_0[15:0],ud_rempty_0, error}) // input wire [17:0] probe0 );
system system_i (.DDR3_0_addr(DDR3_0_addr), .DDR3_0_ba(DDR3_0_ba), .DDR3_0_cas_n(DDR3_0_cas_n), .DDR3_0_ck_n(DDR3_0_ck_n), .DDR3_0_ck_p(DDR3_0_ck_p), .DDR3_0_cke(DDR3_0_cke), .DDR3_0_cs_n(DDR3_0_cs_n), .DDR3_0_dm(DDR3_0_dm), .DDR3_0_dq(DDR3_0_dq), .DDR3_0_dqs_n(DDR3_0_dqs_n), .DDR3_0_dqs_p(DDR3_0_dqs_p), .DDR3_0_odt(DDR3_0_odt), .DDR3_0_ras_n(DDR3_0_ras_n), .DDR3_0_reset_n(DDR3_0_reset_n), .DDR3_0_we_n(DDR3_0_we_n),
.ud_rdata_0(ud_rdata_0), .ud_rde_0(ud_rde_0), .ud_rempty_0(ud_rempty_0), .ud_rvs_0(ud_rvs_0),
.ud_wdata_0(ud_wdata_0), .ud_wde_0(ud_wde_0), .ud_wvs_0(ud_wvs_0),
.init_calib_complete_0(init_calib_complete_0), .wr_rd_clk(wr_rd_clk), .sysclk(sysclk_p)
); endmodule | 
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